1. Field of the Invention
The present invention relates to a chip package, and in particular relates to a chip package having an etching stop layer and a conducting pad protection layer and fabrication method thereof.
2. Description of the Related Art
Wafer level packaging techniques have been developed for chip packaging. After a wafer level package is accomplished, a dicing step is performed between chips to divide them into individual chips. However, exposed conducting pads may be damaged by scrap residue while dicing the packaging layer.
In addition, when etching of a silicon substrate is required, it is an important issue to increase the yield of the chip package by choosing a good etching stop layer.
A novel chip package and fabrication method thereof is needed to address the above issues.